1. Field of the Invention
The present invention relates to a testing method for flash memories, particularly to a diagonal testing method for flash memories.
2. Background of the Invention
The flash memory is a type of programmable and erasable non-volatile memory for recording data. Recently, the requirement for flash memories has been growing rapidly, especially in the application of wireless transmission, automatic equipment, data storage, set-top box and all kinds of multi-media products. The flash memory also has been largely integrated into the SOC (system on a chip) comprising all kinds of logic circuits and memory cores, particularly in the portable product with battery as its power supply. Because the design for SOC tends to have high density, high capacity and high pins, the test time and difficulties are significantly increased. Thus, it becomes an important issue to rapidly and effectively reduce the test time to increase the yield.
Generally, the testing or diagnosis for flash memories is more difficult than conventional memories, particularly due to the disturbance problem during reading and writing cells on the same row or same column. It regulates the disturbance problem and the influence for flash memories in the IEEE 1005 standard. For example, the adjacent memory cells will have undesired charge transfer during the reading or programming of the memory cell in high voltage operation. Compared with the operation of SRAM or DRAM, the flash memory is different in not only writing a single bit or word, but on the contrary, that it can proceed the flash erase on the entire block or chip, such as writing the entire block or chip with logic 1 simultaneously.
Recently, there are different testing methods developed continuously. In which, disturb faults and an optimum algorithm (hereinafter referred to “EF”) are disclosed in M. G. Mohammad, K. K. Saluja, and A. Yap, “Testing Flash Memories,” in Proc. 13th Int. Conf. VLSI Design, January 2000, pp. 406–411. In a paper proposed by M. G. Mohammad and K. K. Saluja, “Flash Memory Disturbances: Modeling and Test,” Proc. IEEE VLSI Test Symp., Marina Del Ray, Calif., April 2001, pp. 218–224, it divides the disturb fault model for flash memories into several coupling faults, and proposes an effective March-like algorithm (hereinafter referred to Flash March) for detecting the coupling faults. In a paper proposed by J. C. Yen, C. F. Wu, K. L. Cheng, Y. F. Chou, C. T. Huang, and C. W. Wu, “Flash Memory Built-in Self-test Using March-Like Algorithms”, Proc. IEEE Int. Workshop on Electronic Design, Test, and Applications (DELTA), Christchurch, January 2002, pp. 137–141, a bit-oriented and word-oriented March-like algorithm (hereinafter referred to March-FT) is disclosed, and is used to cover all the disturb fault types defined in IEEE 1005 standard.
For the operation of the flash memory, the operational speed for erasing is the slowest, the speed for programming is faster, and the speed for reading is the fastest. However, the conventional March-like algorithm includes many writing operations (including erasing and programming), and the test time is too long to make the testing cost relatively high. Therefore, how to design an effective testing method for effectively reducing the required test time without reducing the fault coverage becomes a very important issue.